AVB JPEG Decoder IP for FPGA

The JPEG IP core for FPGAs, developed by SCS, allows compressed Ethernet packages to be received and then decompressed. The decoder has been optimised for low consumption of resources for a Xilinx Spartan6 or Zynq FPGA and is already in use by an OEM and a tier 1 company.

The JPEG Decoder has the following properties:

  • Processing rate of up to 140 MSamples/sec on Spartan6 FPGA
  • 12Bit / 8Bit version available
  • Four Huffmann tables (fixed or extracted from header)
  • Up to 8 quantisation tables
  • Support to decode several interleaved image stripes
  • 3 color components
  • Support 1 scan configuration and YUV 4:2:0 (Different format on request)
  • Supports any image size up to 64kx64k
  • Supports restart markers

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