Initial Situation
A high-resolution 4D radar processes enormous amounts of data in real time and thus places high demands on computing power. The algorithm developed by ZF therefore had to be optimally distributed across the different computing units of a modern MPSoC. Computationally intensive pre-processing, such as FFT and peak detection, runs on the FPGA, while subsequent processing steps like tracking can be executed on the ARM core. SCS had to optimize, implement, and test this architecture under the requirements of functional safety.
SCS’s Contribution
SCS transferred ZF’s radar algorithms into a performance-optimized Zynq UltraScale+ architecture and supported the implementation from FPGA design, embedded software, and testing to documentation for functional safety.
Result
ZF had a functional prototype for initial tests within a very short time. The FPGA implementation largely utilizes the available computing power of the MPSoC while meeting the requirements for functional safety and traceability. With 192 channels and a range of 350 meters, the 4D radar enables highly detailed scene and object detection for automated driving functions. For example, a vehicle on the highway can detect the end of a traffic jam under a bridge early and brake in time. The system has since been further developed for series production.
192 channels
approximately 16 times higher resolution than a typical vehicle radar.
350 m
range for highly detailed scene and object detection.
ISO 26262 ASIL B
compliant development for functional safety.
